Delay Optimization and Power Optimization of 4-Bit ALU Designed in FS-GDI Technique

Abstract

In this thesis proposed a reduction of delay, leakage current, leakage power. First find out the leakage current and leakage power. This thesis uses a gate diffusion input technique. By using this no of transistor is reduced. If number of transistor is reduced, area is also reduced, leakage current also affected.

To study all parameter in this thesis uses a 2x1 MUX, 4x1MUX,16x1 MUX and ALU. Applying a GDI technique and also implemented by using a CMOS technique. Then do comparisons on GDI and CMOS technique and do a capacitance calculation.

To implement all those things use a microwind 3.1 and DSCH 2.0. It is an Electronic Design Automation (EDA) environment that allows implementing a integrating in a single framework different applications and tools, allowing supporting all the stages of IC design and verification from a single environment. The resulting layout must verify some geometric rules dependent on the technology (design rules). Now checked with a Design Rule Checker (DRC) to find any error in the layout diagram and them simulation is performed.

In implementing and do a comparisons of GDI and CMOS technique we get a 75% advantage in 2x1 MUX in counting the number of transistor. In 4x1 MUX we get again a 75% gain in the number of transistor. In 8x1 MUX, give a 78% benefits in the number of transistor. In 16x1 MUX, give a 81% benefits in the number of transistor. In 1 bit ALU give a 54% benefits in the number of transistor.

If related power consumption, get a 74% benefits in comparisons of GDI and CMOS technique in 2x1 MUX. In 4x1mux give the advantage of 79% in the power consumption in comparisons of GDI and CMOS technique. In 8x1mux give the advantage of 78% in the power consumption in comparisons of GDI and CMOS technique. In 16x1mux give the advantage of 79% in the power consumption comparisons of GDI and CMOS technique. In bit ALU give the advantage of 64% in the power consumption in comparisons of GDI and CMOS technique.