High Speed Area Efficient VLSI Architecture for DCT and DHT Algorithm

Authors

  • Sonam Nema M. Tech Scholar, Department of Electronics and Communication Engineering, SAM College of Engineering & Technology, Bhopal, M.P., India
  • Adesh Gour Professor, Department of Electronics and Communication Engineering, SAM College of Engineering & Technology, Bhopal, M.P., India

DOI:

https://doi.org/10.24113/ijoscience.v3i5.53

Keywords:

Discrete Cosine Transform, Discrete Fourier Transform, Coordinate Rotation Digital Computer

Abstract

Low-power layout is one of the most vital challenges to maximize battery life in portable devices and to save the energy during simulation operation. Image and video compressor is widely used in Discrete Cosine Transform (DCT). Many types of techniques are used in design discrete cosine transform (DCT). Multiplier and adder are two main components in design to DCT, Loeffer (1989) have developed a new architecture DCT, it consists of 11 multiplications and 29 additions. By now a day we required low chip area and fast speed algorithm, but the multiplier consumed large area compared to adder. We are designed to multiplier less CORDIC (Coordinate Rotation Digital Computer) algorithm based on DCT. CORDIC is a main component of shift and add for rotation vector and plan which is usually used for calculation of trigonometric functions. CORDIC algorithm is efficient area and delay compared to existing algorithms. All design are implementation Xilinx 14.1i and verified the result.

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References

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Published

05/31/2017

How to Cite

Nema, S. ., & Gour, A. (2017). High Speed Area Efficient VLSI Architecture for DCT and DHT Algorithm. SMART MOVES JOURNAL IJOSCIENCE, 3(5), 18–22. https://doi.org/10.24113/ijoscience.v3i5.53

Issue

Vol. 3 No. 5 (2017): Volume III, Issue V May 2017

Section

Articles

License

Copyright (c) 2017 SONAM NEMA, ADESH GOUR

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