High Speed Area Efficient VLSI Architecture for DCT and DHT Algorithm


  • Sonam Nema M. Tech Scholar, Department of Electronics and Communication Engineering, SAM College of Engineering & Technology, Bhopal, M.P., India
  • Adesh Gour Professor, Department of Electronics and Communication Engineering, SAM College of Engineering & Technology, Bhopal, M.P., India




Discrete Cosine Transform, Discrete Fourier Transform, Coordinate Rotation Digital Computer


Low-power layout is one of the most vital challenges to maximize battery life in portable devices and to save the energy during simulation operation. Image and video compressor is widely used in Discrete Cosine Transform (DCT). Many types of techniques are used in design discrete cosine transform (DCT). Multiplier and adder are two main components in design to DCT, Loeffer (1989) have developed a new architecture DCT, it consists of 11 multiplications and 29 additions. By now a day we required low chip area and fast speed algorithm, but the multiplier consumed large area compared to adder. We are designed to multiplier less CORDIC (Coordinate Rotation Digital Computer) algorithm based on DCT. CORDIC is a main component of shift and add for rotation vector and plan which is usually used for calculation of trigonometric functions. CORDIC algorithm is efficient area and delay compared to existing algorithms. All design are implementation Xilinx 14.1i and verified the result.


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Doru Florin Chiper, Senior Member, IEEE, “A Novel VLSI DHT Algorithm for a Highly Modular and Parallel Architecture”, IEEE Transactions on Circuits and Systems—Ii: Express Briefs, Vol. 60, NO. 5, May 2013.

Mamatha I, Nikhita Raj J, Shikha Tripathi, Sudarshan TSB, “Systolic Architecture Implementation of 1D DFT and 1D DCT”, 978-1-4799-1823-2/15/$31.00 ©2015 IEEE.

Liyi Xiao Member, IEEE and Hai Huang, “Novel CORDIC Based Unified Architecture for DCT and IDCT”, 2012 International Conference on Optoelectronics and Microelectronics (ICOM) 978-1-4673-2639-1/12/$31.00 ©2012 IEEE.

Shymna Nizar N.S,Abhila and R Krishna, “An Efficient Folded Pipelined Architecture For Fast

Fourier Transform Using Cordie Algorithm”, 2014 IEEE International Conference on Advanced Communication Control and Computing Technologies (lCACCCT) IEEE.

E. Jebamalar Leavline, S.Megala2 and D.Asir Antony Gnana Singh, “CORDIC Iterations Based Architecture for Low Power and High Quality DCT”, 2014 International Conference on Recent Trends in Information Technology 978-1-4799-4989-2/14/$31.00 © 2014 IEEE.

Satyasen Panda, “Performance Analysis and Design of a Discreet Cosine Transform processor Using CORDIC algorithm”, 2008-2010.

Keshab K. Parhi, “VLSI Digital Signal Processing Systems, design and implementation”, Wiley.


Yuan-Ho Chen et al, “A High Performance Video Transform Engine by Using Space- Time Scheduling Strategy”, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 4, APRIL 2012.

Xue Liu, Feng Yu, Ze-ke Wang, " A Pipelined Architecture for Normal I/O Order FFT", Journal of Zhejiang University-SCIENCE C (Comput & Electron) , vol.12, no.1, 2011 , pp::76-82.

Weihua Zheng, Kenli Li, Keqin Li, "A Fast Algorithm Based on SRFFT for Length N=qx2m DFTs", IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 61, no.2, 2014, pp: 110-114.

Weihua Zheng, Kenli Li, and Keqin Li," A Fast Algorithm Based on SRFFT for Length N = q × 2m DFTs , IEEE Trans. Circuits Syst.II, Exp. Briefs, vol. 61, no. 2, pp.110-114, Feb. 2014




How to Cite

Nema, S. ., & Gour, A. (2017). High Speed Area Efficient VLSI Architecture for DCT and DHT Algorithm. SMART MOVES JOURNAL IJOSCIENCE, 3(5), 18–22. https://doi.org/10.24113/ijoscience.v3i5.53