CMOS Implementation of 5T SRAM with Low Power Dissipation

Authors

  • Rajesh Kumar M.Tech Scholar, Vidhyapeeth Institute of Science & Technology, Bhopal (MP) India
  • Swati Gupta

DOI:

https://doi.org/10.24113/ijoscience.v7i8.400

Keywords:

SRAM, MICROWIND, N-MOS, C-MOS

Abstract

SRAM is a very fast memory with low power consumption. The main objective of this work is to perform a 64-digit SRAM with 90 nm innovation. Execution depended on a granular perspective. SRAM's base module is similar to an N-MOS inverter, flip-flop, and semiconductor. We design this module according to the configuration rule of the ? format. Using Harvard technology, SRAM can easily retrieve information from memory. To create advanced rational circuits, it is important to see how an SRAM is assembled and how it works. The bottom line is that with 0.12 micron 90nm technology, we are developing a 5T SRAM and we can read and write. It is a fundamental part of a computer's central processing unit. RAM is a building block made up of several circuits. The 64-bit SRAM reader was developed with MICROWIND and DSCH2. With the MICROWIND program, the developer can design and simulate an integrated circuit at the physical description level. DSCH2 allows switching of digital logic design.

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Author Biography

Swati Gupta

  • John R Hu, James Chen “Systematic co-optimization from chip design, process technology to systems for GPU AI chip”, 2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 16-19 April 2018.
  • Horowitz, “Computing’s energy problem (and what we can do about it),” in ISSCC Digest of Technical Papers, Feb. 2014, pp. 10–14.
  • Taylor, “Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse,” in Proc. of the Design Automation Conf., Jun. 2012, pp. 1131–1136.
  • Chen et al., “DianNao: A Small-footprint High-throughput Accelerator for Ubiquitous Machine-learning,” in Proc. of Intl. Conf. on Architectural Support for Programming Languages and Operating Systems, 2014, pp. 269–284.
  • Wang, K. H. Lee, and N. Verma, “Hardware specialization in lowpower sensing applications to address energy and resilience,” Journal of Signal Processing Systems, vol. 78, no. 1, pp. 49–62, 2014.
  • Momose, Tatsuya Kaneko and Tetsuya Asai “Systems and circuits for AI chips and their trends” japanese Journal of Applied Physics, Volume 59, Number 5, 2020.
  • Chen, YuanXie “A Survey of Accelerator Architectures for Deep Neural Networks” Engineering Volume 6, Issue 3, March 2020, Pages 264-274.
  • Tso-Bing Juang,, Cong-Yi Lin and Guan-Zhong Lin “Area-Delay Product Efficient Design for Convolutional Neural Network Circuits Using Logarithmic Number Systems” ISOCC 2018.
  • Grewal, S. Areibi, M. Westrik, Z. Abuowaimer and B. Zhao, "Automatic Flow Selection and Quality-of-Result Estimation for FPGA Placement," 2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Lake Buena Vista, FL, 2017, pp. 115-123.
  • J. Chan, P. Ho, A. B. Kahng, P. Saxena, “Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning,” Proceedings of the 2017 ACM on International Symposium on Physical Design (ISPD 17), pp. 15-21.

 

 

 

References

John R Hu, James Chen “Systematic co-optimization from chip design, process technology to systems for GPU AI chip”, 2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 16-19 April 2018.

M. Horowitz, “Computing’s energy problem (and what we can do about it),” in ISSCC Digest of Technical Papers, Feb. 2014, pp. 10–14. DOI: https://doi.org/10.1109/ISSCC.2014.6757323

M. Taylor, “Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse,” in Proc. of the Design Automation Conf., Jun. 2012, pp. 1131–1136. DOI: https://doi.org/10.1145/2228360.2228567

T. Chen et al., “DianNao: A Small-footprint High-throughput Accelerator for Ubiquitous Machine-learning,” in Proc. of Intl. Conf. on Architectural Support for Programming Languages and Operating Systems, 2014, pp. 269–284. DOI: https://doi.org/10.1145/2541940.2541967

Z. Wang, K. H. Lee, and N. Verma, “Hardware specialization in lowpower sensing applications to address energy and resilience,” Journal of Signal Processing Systems, vol. 78, no. 1, pp. 49–62, 2014. DOI: https://doi.org/10.1007/s11265-014-0931-y

H. Momose, Tatsuya Kaneko and Tetsuya Asai “Systems and circuits for AI chips and their trends” japanese Journal of Applied Physics, Volume 59, Number 5, 2020. DOI: https://doi.org/10.35848/1347-4065/ab839f

Y. Chen, YuanXie “A Survey of Accelerator Architectures for Deep Neural Networks” Engineering Volume 6, Issue 3, March 2020, Pages 264-274. DOI: https://doi.org/10.1016/j.eng.2020.01.007

Tso-Bing Juang,, Cong-Yi Lin and Guan-Zhong Lin “Area-Delay Product Efficient Design for Convolutional Neural Network Circuits Using Logarithmic Number Systems” ISOCC 2018. DOI: https://doi.org/10.1109/ISOCC.2018.8649961

G. Grewal, S. Areibi, M. Westrik, Z. Abuowaimer and B. Zhao, "Automatic Flow Selection and Quality-of-Result Estimation for FPGA Placement," 2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Lake Buena Vista, FL, 2017, pp. 115-123. DOI: https://doi.org/10.1109/IPDPSW.2017.54

W. J. Chan, P. Ho, A. B. Kahng, P. Saxena, “Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning,” Proceedings of the 2017 ACM on International Symposium on Physical Design (ISPD 17), pp. 15-21. DOI: https://doi.org/10.1145/3036669.3036681

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Published

08/19/2021

How to Cite

Kumar, R., & Gupta, S. . (2021). CMOS Implementation of 5T SRAM with Low Power Dissipation. SMART MOVES JOURNAL IJOSCIENCE, 7(8), 19–29. https://doi.org/10.24113/ijoscience.v7i8.400

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