Less Power Consumption Based Low Delay Based 9-Transistors Based Full Adder

Authors

  • Anurag Kothari Depart of Electronics & Communication Engineering, Mittal Institute of Technology Bhopal, M.P., India
  • Achint Chugh Depart of Electronics & Communication Engineering, Mittal Institute of Technology, Bhopal, M.P., India

DOI:

https://doi.org/10.24113/ijoscience.v3i6.36

Keywords:

Power consumption, Delay, SUM, Carry, Cin, Cout, Full Adder

Abstract

 Circuit model of computer is widely accepted as a better abstraction of computational process across the world. The building block of a circuit is the logic gates which are the main information processing units. But this gates use higher power consumption. To reduce this power consumption researcher go on transistors. Transistors based design will gain increasing interest in industrial applications if they satisfy the following requirements: Less power requirement and reduced time with reduced design effort. The aim of this work is to contribute to reach these requirements for the design of full adders. In this paper, we present efficient full adder implementations using the transistors. The proposed design is based on a novel NMOS and PMOS transistors.

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Published

07/31/2017

How to Cite

Kothari, A. ., & Chugh, A. . (2017). Less Power Consumption Based Low Delay Based 9-Transistors Based Full Adder. SMART MOVES JOURNAL IJOSCIENCE, 3(6), 1–5. https://doi.org/10.24113/ijoscience.v3i6.36