Estimation of Delay to Consider Leakage in CMOS VLSI Circuit

Adil Tanveer

doi:10.24113/ijoscience.v4i11.205

Authors

Adil Tanveer Department of Microelectronics and VLSI Technocrates Institute of Technology Bhopal, M.P, India

DOI:

https://doi.org/10.24113/ijoscience.v4i11.205

Abstract

In digital CMOS circuits, parametric yield improvement may be achieved by reducing the variability of performance and power consumption of individual cell instances. In recent years, increasing demand of portable digital systems has led to rapid and innovative development in the field of low power design. Such improvement of variation robustness can be attained by evaluating parameter variation impact at gate level. Statistical characterization of logic gates are usually obtained by computationally expensive electrical simulations. An efficient gate delay variability estimation method is proposed for variability-aware design. As the technology scaled down to deep nanometer level, the power supply, threshold (Vt) and device geometry gets reduces. The sub threshold current continue to increase exponentially, when the Vt of the device is reduced. The leakage current is now a dominant part of total power dissipation as the technology scales down. The proposed method has been applied to different topologies (transistor network arrangements) and CMOS gates, and it has been compared to Monte Carlo simulations for data validation, resulting in computation time savings.

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