Delay Optimization and Power Optimization of 4-Bit ALU Designed in FS-GDI Technique

In this thesis proposed a reduction of delay, leakage current, leakage power. First find out the leakage current and leakage power. This thesis uses a gate diffusion input technique. By using this no of transistor is reduced. If number of transistor is reduced, area is also reduced, leakage current also affected. To study all parameter in this thesis uses a 2x1 MUX, 4x1MUX,16x1 MUX and ALU. Applying a GDI technique and also implemented by using a CMOS technique. Then do comparisons on GDI and CMOS technique and do a capacitance calculation. To implement all those things use a microwind 3.1 and DSCH 2.0. It is an Electronic Design Automation (EDA) environment that allows implementing a integrating in a single framework different applications and tools, allowing supporting all the stages of IC design and verification from a single environment. The resulting layout must verify some geometric rules dependent on the technology (design rules). Now checked with a Design Rule Checker (DRC) to find any error in the layout diagram and them simulation is performed. In implementing and do a comparisons of GDI and CMOS technique we get a 75% advantage in 2x1 MUX in counting the number of transistor. In 4x1 MUX we get again a 75% gain in the number of transistor. In 8x1 MUX, give a 78% benefits in the number of transistor. In 16x1 MUX, give a 81% benefits in the number of transistor. In 1 bit ALU give a 54% benefits in the number of transistor. If related power consumption, get a 74% benefits in comparisons of GDI and CMOS technique in 2x1 MUX. In 4x1mux give the advantage of 79% in the power consumption in comparisons of GDI and CMOS technique. In 8x1mux give the advantage of 78% in the power consumption in comparisons of GDI and CMOS technique. In 16x1mux give the advantage of 79% in the power consumption comparisons of GDI and CMOS technique. In bit ALU give the advantage of 64% in the power consumption in comparisons of GDI and CMOS technique.


ABSTRACT
In this thesis proposed a reduction of delay, leakage current, leakage power. First find out the leakage current and leakage power. This thesis uses a gate diffusion input technique. By using this no of transistor is reduced. If number of transistor is reduced, area is also reduced, leakage current also affected. To study all parameter in this thesis uses a 2x1 MUX, 4x1MUX,16x1 MUX and ALU. Applying a GDI technique and also implemented by using a CMOS technique. Then do comparisons on GDI and CMOS technique and do a capacitance calculation. To implement all those things use a microwind 3.1 and DSCH 2.0. It is an Electronic Design Automation (EDA) environment that allows implementing a integrating in a single framework different applications and tools, allowing supporting all the stages of IC design and verification from a single environment. The resulting layout must verify some geometric rules dependent on the technology (design rules). Now checked with a Design Rule Checker (DRC) to find any error in the layout diagram and them simulation is performed. In implementing and do a comparisons of GDI and CMOS technique we get a 75% advantage in 2x1 MUX in counting the number of transistor. In 4x1 MUX we get again a 75% gain in the number of transistor. In 8x1 MUX, give a 78% benefits in the number of transistor. In 16x1 MUX, give a 81% benefits in the number of transistor. In 1 bit ALU give a 54% benefits in the number of transistor. If related power consumption, get a 74% benefits in comparisons of GDI and CMOS technique in 2x1 MUX. In 4x1mux give the advantage of 79% in the power consumption in comparisons of GDI and CMOS technique. In 8x1mux give the advantage of 78% in the power consumption in comparisons of GDI and CMOS technique. In 16x1mux give the advantage of 79% in the power consumption comparisons of GDI and CMOS technique. In bit ALU give the advantage of 64% in the power consumption in comparisons of GDI and CMOS technique.

I.INTRODUCTION
Reducing power losses in VLSI circuits is becoming one of the most significant challenges in the semiconductor industry. Performance optimization techniques are applied to all semiconductor design levels. Advanced processors offer numerous architectural improvements, such as branch forecasting, software hardware cooptimization, and the use of multiple cores in a single processor [3]. Portability requirements for laptops and other portable devices significantly limit size and power consumption. Although battery technology is constantly improving and processors and displays are improving rapidly in terms of power consumption, battery life and weight are factors that have a significant impact on the way laptops can be used for. These devices often require real-time processing functions and therefore require high throughput. [4] Energy consumption becomes the limiting factor for the range of functions of these devices. The wider and continuous use of network services will only exaggerate this problem because communication consumes a relatively high amount of energy. The gradual downsizing of the technology has led to the use of lower supply voltages for CMOS circuits, which affects lower threshold voltages to improve performance [5]. As the channel length decreases for future technology generations, the threshold voltage and gate oxide thickness are also reduced to keep pace with performance [6,7]. A lower threshold voltage leads to an exponential increase in the leakage current because the transistors cannot be completely turned off. In a CMOS circuit, total power loss includes dynamic and static components. The components of static power loss are losses below the threshold, junction losses, gate oxide losses, networkinduced drainage losses and breakage losses. [8,9] [2]. Afshin Abdollahi, Farzan Fallah and Massoud Pedram offer a reduction of the leakage current in the CMOS-VLSI circuits thanks to the input vector control, in which the first part of this work describes two execution mechanisms to reduce the leakage current of a CMOS circuit. In either case, the system or environment should generate a "sleep" signal which can be used to indicate that the circuit is in sleep mode. In the first method, the "sleep" signal is used to move a new set of external inputs and pre-selected internal signals in the circuit in order to define the logical values of all the internal signals so that the sum of the leakage current is a minimized circuit. III.METHODOLOGY We have proposed a loss reduction technique. Here, the gate diffusion input is used to reduce losses and dynamic power in a circuit. The GDI approach allows the implementation of a large number of complex logic functions with only two transistors. This method is suitable for the design of low-power fast circuits using a small number of transistors.

=
Where C = capacitance between the conductors.
The dispersion capability can normally be ignored at low frequencies, but it can pose a major problem with high frequency circuits. In circuits with an extended frequency response, the parasitic capacitance between the output and the input can act as a feedback path, as a result of which the circuit oscillates at high frequency. These unwanted vibrations are called parasitic vibrations.

1) GATE DIFFUSION INPUT
The grid diffusion input (GDI) is a new technique for developing low power dissipation. This technique allows you to reduce power loss, the number of transistors and the surface of digital circuits. This approach allows you to implement various complex logic functions with only two transistors. GDI suggests and compares with traditional CMOS. The comparison between the number of GDI transistors and CMOS is presented. The simulation result shows that the proposed GDI has better performance in terms of power dissipation and number of transistors than the CMOS design.
Here we used a circuit diagram to discuss another type of  Table -1Some logic functions that can be implemented with a single GDI cell

3) LIMITATIONS OF GDI TECHNIQUE
GDI MUX has only one limitation that it requires additional circuitry to restore its full swing.

4) BSIM -BERKELEY SHORT-CHANNEL IGFET MODEL
The newly developed LEVEL 4 model (Berkeley or BSIM short channel IGFET model) is analytically simple and is based on a limited number of parameters that are normally extracted from experimental data. Its precision and efficiency make it one of the most popular MOSFET models today, especially in the microelectronics sector. Model features include: 1. Continuous and differentiable I-V characteristics below the threshold, linear and saturation intervals for good convergence 2. Sensitivity of parameters such as Vt to the length and width of the transistor 3. Detailed model of the threshold voltage which includes the body effect and the lowering of the barrier induced by the discharge 4. Saturation speed, reduced mobility and other short channel effects 5. Models with multiple door capability 6. Models of diffusion capacity and resistance 7. Network loss models (in BSIM 4)

5) DESIGN RULE
Cadence is an EDA (Electronic Design Automation) environment that allows you to integrate different applications and tools into a single framework and supports all phases of design and verification of integrated circuits in a single environment. These tools are very generic and support various production technologies. When a particular technology is selected, numerous configuration and technology-related files are used to customize the Cadence environment. This set of files is commonly known as a design kit. First, a schematic view of the circuit is created with the Cadence Composer circuit diagram editor.

6) LSW
The Layer Selection Window (LSW) lets the user select different layers of the mask layout. Virtuoso will always use the layer currently selected in the LSW for editing. The LSW can also be used to restrict the type of layers that are visible or selectable. To select a layer, simply click on the desired layer within the LSW.

IV. RESULTS 1) IMPLEMENTATION OF 2X1 MULTIPLEXER WITH GDI TECHNIQUE
To implement 2-to-1 multiplexer by GDI technique in which one NMOS and one PMOS are used with two inputs is applied in two terminal and selection line as a thread terminal as shown in figure 2.   figure 4 shows the transistor level representation of the 4-to-1 multiplexer with GDI technique in which 4 inputs I0, I1, I2, I3 and two selection lines S0 and S1.   Here implementing a 2x4 decoder, taking a 2 input f0, f1 and output will be d0, d1, d2, d3. Output d0 gives the output when the input combination 00 is selected and d1 gives the output when the input combination 01 is selected. Output d2 gives the output when the input combination 10 is selected and d3 gives the output when the input combination 11 is selected. Transistor level representation of DECODER with GDI technique is shown in figure 4.6. www.ijoscience.com 5 Figure 8: Transistor level representation of AND gate with GDI technique (iii)OR GATE OR gate is a basic logic gate it has the property that if any input is high, output is high and if both input is low, output is low. To implement OR gate with GDI technique used a 2 transistor in which P terminal is connected with input B and G terminal connected with input A and N terminal is connected with supply. Transistor level representation of OR gate with GDI technique is shown in figure 4.8. Figure 9: Transistor level representation of OR gate with GDI technique (iv)NOT GATE Transistor level representation of NOT gate with GDI technique is shown in figure 4.9 in which P terminal is connected with supply and G terminal is connected with the input A and N terminal is connected with ground and output is connected with drain of the transistor. To implement NOT gate with the GDI technique used a two transistor.   with GDI technique (vi) FULL ADDER Full adder is a combinational circuits it performs the addition operation. Figure 12 shows a Transistor level representation of Full adder with GDI technique in which used an 18 transistor, 9 for NMOS and 9 for PMOS transistor.    Figure 17 shows layout representation of 4 -to-1 MUX with GDI technique in which indicate the operation and their Voltage vs. time simulation of 4 -to-1 MUX with GDI technique is shows in figure 18. Figure 19 shows a Voltage vs. current simulation in 4 -to-1 MUX with GDI technique.    The voltage vs. current simulation in 16X1 MUX with GDI technique is shown in figure 25 in which present a behavior of current with respect to voltage. Figure 26 shows a layout representation of 1 BIT ALU with GDI technique in which shows a input f0, f1, A and B and gives the output OUT and CARRYOUT.            In implementing and do a comparisons of GDI and CMOS technique we get a 75% advantage in 2x1 MUX in counting the number of transistor. In 4x1 MUX we get again a 75% gain in the number of transistor. In 8x1 MUX, give a 78% benefits in the number of transistor. In 16x1 MUX, give a 81% benefits in the number of transistor. In 1 bit ALU give a 54% benefits in the number of transistor.

10) LAYOUT OF 1-BIT ALU
In reference of leakage current or leakage power, get a 94% benefits in comparisons of GDI and CMOS technique in 2x1 MUX. In 4x1MUX give the advantage of 85% in the leakage current in comparisons of GDI and CMOS technique. In 8x1MUX give the advantage of 95% in the leakage current in comparisons of GDI and CMOS technique. In 16x1MUX give the advantage of 74% in the leakage current comparisons of GDI and CMOS technique. In bit ALU give the advantage of 58% in the leakage current in comparisons of GDI and CMOS technique. If related power consumption, get a 74% benefits in comparisons of GDI and CMOS technique in 2x1 MUX. In 4x1MUX give the advantage of 79% in the power consumption in comparisons of GDI and CMOS technique. In 8x1MUX give the advantage of 78% in the power consumption in comparisons of GDI and CMOS technique. In 16x1MUX give the advantage of 79% in the power consumption comparisons of GDI and CMOS technique. In bit ALU give the advantage of 64% in the power consumption in comparisons of GDI and CMOS technique.
V.FUTURE WORK The power dissipation of electronic products has become a major problem in connection with the huge growth of laptops and wireless communications in recent years. Since the power consumption is directly proportional to the square of the supply voltage, the MOS transistor has been scaled down to maintain performance with the supply voltage reduced. The threshold voltage of the transistor is also reduced to avoid a short channel effect, which causes a significant increase in the leakage currents when the transistor evolves into nanometric dimensions. Backup power represents a significant part of the total energy consumption of integrated circuits.